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ECE 484 - Advanced Digital Systems Design Lecture 3 – Basic Language Constructs of VHDL

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ECE 484 - Advanced Digital Systems Design Lecture 3 – Basic Language Constructs of VHDL

HQ U.S. Air Force Academy. I n t e g r i t y - S e r v i c e - E x c e l l e n c e. ECE 484 - Advanced Digital Systems Design Lecture 3 – Basic Language Constructs of VHDL. Capt Michael Tanner Room 2F46A 333-6766. Lesson Outline. Basic VHDL Program Lexical Elements and Program Format

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ECE 484 - Advanced Digital Systems Design Lecture 3 – Basic Language Constructs of VHDL

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HQ U.S. Air Force Academy I n t e g r i t y - S e r v i c e - E x c e l l e n c e ECE 484 - Advanced Digital Systems DesignLecture 3 – Basic Language Constructs of VHDL Capt Michael TannerRoom 2F46A333-6766
Lesson Outline Basic VHDL Program Lexical Elements and Program Format VHDL Objects Data Types and Operators Synthesis Guidelines
Basic VHDL Program
Design Unit • Building blocks in a VHDL program • Each design unit is analyzed and stored independently • Types of design unit: • entity declaration • architecture body • package declaration • package body • configuration
Entity Declaration entityentity_nameis port( port_names:mode data_type; port_names:mode data_type; ... port_names:mode data_type ); endentity_name; entityeven_detectoris port( a :in std_logic_vector(2 downto 0); even :out std_logic; ); endeven_detector; • Simplified syntax • Mode: • in: flow into the circuit • out: flow out of the circuit • inout: bi-directional flow
Common Mistake with Mode ... architecture correct ofentity_nameis signalx_i:std_logic; begin x_i<=a and b; x <=x_i; y <=notx_i; end correct; entitymode_demois port( a, b:in std_logic; x, y :out std_logic; ); endmode_demo; architecturewrong ofmode_demois begin x <=aand b; y <=notx; end wrong;
Architecture Body architecturearch_nameofentity_nameis declarations; begin concurrent statement; concurrent statement; concurrent statement; ... endarch_name; architecturesop_archofeven_detectoris signal p1, p2, p3, p4 :std_logic; begin even <=(p1 or p2)or(p3 or p4); p1 <=(not a(2))and(not a(1))and(not a(0)); p2 <=(not a(2))and a(1)and a(0); p3 <= a(2)and(not a(1))and a(0); p4 <= a(2)and a(1)and(not a(0)); endsop_arch; Simplified syntax An entity declaration can be associated with multiple architecture bodies
Other Design Units 1 libraryieee; 2 useieee.std_logic_1164.all; • Invoke library named IEEE • Make std_logic_1164 visible to all design units in current file • Package declaration/body - collection of commonly used items: • Data Types • Subprograms • Components • Configuration – specify which architecture body is to be bound with the entity declaration • VHDL Library – A place to store the analyzed design units • Normally mapped to a folder on host computer • Default library: "work" • Library "IEEE" is used for many IEEE packages
Processing of VHDL Code • Analysis • Performed on "design unit" basis • Check the syntax and translate the unit into an intermediate form • Store design unit in a library • Elaboration • Bind architecture body with entity • Substitute the instantiated components with architecture description • Create a "flattened"' description • Execution • Simulation or synthesis
Lexical Elements and Program Format
Lexical Elements • Basic syntactical units in a VHDL program • Types of elements: • Comments • Identifiers • Reserved words • Numbers • Characters • Strings
Comments --******************************************* -- Example to show the caveot of the out mode --******************************************* architecture correct ofentity_nameis signalx_i:std_logic; -- Internal signal begin x_i<=a and b; x <=x_i; -- Connect the internal signal to the output y <=notx_i; end correct; Starts with -- Comments for the remainder of the line Added for program clarity and documentation VHDL 2008 supports C-style block commenting /* ... */
Identifier • Identifier is the name of an object • Basic rules: • Can only contain alphabetic letters, decimal digits and underscore • The first character must be a letter • The last character cannot be an underscore • Two successive underscores are not allowed • Valid: A10, next_state, NextState • Invalid: sig#3, _X10, 7segment, X10_, hi_ _there • VHDL is case insensitive: {nextstate, NextState, NEXTSTATE, nEXTsTATE} are all the same
Reserved Words
Numbers, Characters, and Strings • Number: • Integer: 0, 1234, 98E7 • Real: 0.0, 1.23456 or 9.87E6 • Base 2: 2#101101# • Character: • 'A', 'Z', '1' • Strings • "Hello", "101101" • Note: • 0 and '0' are different • 2#101101# and "101101" are different
Program Format architecturecorrect ofentity_nameis signalx_i:std_logic; begin x_i<= a and b; x <=x_i; y <=notx_i; end correct; architecturecorrect ofentity_nameis signalx_i:std_logic; begin x_i<= a and b;x <=x_i;y <=notx_i; endcorrect; • VHDL is "free-format": blank space, tab, new-line (i.e., "white space") can be freely inserted • The following are the same:
VHDL Objects
Objects • A named item that hold a value of specific data type • Four kinds of objects • Signal • Variable • Constant • File (cannot be synthesized) • Related construct • Alias
Signal Declared in the architecture body's declaration section Signal declaration:signalsig1, sig2, ... : data_type; Signal assignment: signal_name <= projected_waveform; Ports in entity declaration are considered as signals Can be interpreted as wires or "wires with memory" (e.g., FFs, latches etc.)
Variable Declared and used inside a process Variable declaration:variablevar1, var2, ... : data_type; Variable assignment: variable_name := value_expression; Contains no "timing info" (immediate assignment) Used as in traditional PL: a "symbolic memory location" where a value can be stored and modified No direct hardware counterpart
Constant constant BUS_WIDTH :integer:=32; constant BUS_BYTDL :integer:= BUS_WIDTH /8; Value cannot be changed Constant declaration:constantconst_name, ... : data_type := value_expression; Used to enhance readability
Constant Example:Avoid Hard Literals architecture beh1_arch ofeven_detectoris signal odd :std_logic; begin ... tmp:='0'; for i in2downto0loop tmp:=tmpxor a(i); endloop; Versus • architecture beh1_arch ofeven_detectoris • signal odd :std_logic; • constant BUS_WIDTH :integer:=3; • begin • ... • tmp:='0'; • for i in(BUS_WIDTH-1)downto0loop • tmp:=tmpxor a(i); • endloop; • ...
Alias signal word :std_logic_vector(15downto0); alias op :std_logic_vector(6downto0)is word(15downto9); alias reg1 :std_logic_vector(2downto0)is word(8downto6); alias reg2 :std_logic_vector(2downto0)is word(5downto3); alias reg3 :std_logic_vector(2downto0)is word(2downto0); Not an object Alternative name for an object Used to enhance readability
Data Types and Operators
Data Types and Operators Standard VHDL IEEE1164_std_logic package IEEE numeric_std package
Data Type • Definition of data type • A set of values that an object can assume. • A set of operations that can be performed on objects of this data type. • VHDL is a strongly-typed language • an object can only be assigned with a value of its type • Error: int_var := char_var; • Correct: int_var := to_integer(char_var); • only the operations defined with the data type can be performed on the object
Data Types in Standard VHDL • integer: • Minimal range: -(2^31-1) to 2^31-1 • Two subtypes: natural, positive • boolean: (false, true) • bit: ('0', '1') • Not capable enough • bit_vector: a one-dimensional array of bit
Operators in Standard VHDL
Operators in Standard VHDL
IEEE std_logic_1164 package • What's wrong with bit? • New data type: std_logic, std_logic_vector • std_logic: 9 values: ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-') • '0', '1': forcing logic 0' and forcing logic 1 • 'Z': high-impedance, as in a tri-state buffer. • 'L' , 'H': weak logic 0 and weak logic 1, as in wired logic • 'X', 'W': "unknown" and "weak unknown" • 'U': for uninitialized • '-': don't-care.
IEEE std_logic_1164 package libraryieee; use ieee.std_logic_1164.all; • std_logic_vector • an array of elements with std_logic data type • Implies a bus • Example declarationsignala:instd_logic_vector(7downto0); • Another form (less desired)signal a:instd_logic_vector(0 to7); • Need to invoke package to use the data type:
IEEE std_logic_1164 package:Overloaded Operators Which standard VHDL operators can be applied to std_logic and std_logic_vector? Overloading: same operator of different data types Overloaded operators in std_logic_1164 package
IEEE std_logic_1164 package:Conversion Functions signal s1, s2, s3 :std_logic_vector(7downto0); signal b1, b2:bit_vector(7downto0); s1 <=to_stdlogicvector(b1); b2 <=to_bitvector(s1 and s2); s3 <=to_stdlogicvector(b1)or s2; s3 <=to_stdlogicvector(b1 orto_bitvector(s2)); Provides functions to convert between data types
Array Data Type Operators • Relational operators for array • operands must have the same element type but their lengths may differ • Two arrays are compared element by element, form the left most element • All following returns true • "011"="011", "011">"010", "011">"00010", "0110">"011" • Concatenation operator (&) y <= "00" & a(7 downto 2); y <= a(7) & a(7) & a(7 downto 2); y <= a(1 downto 0) & a(7 downto 2);
Array Aggregate • Aggregate is a VHDL construct to assign a value to an array-typed object a <= "10100000"; a <= (7 => '1', 6 => '0', 0 => '0', 1 => '0', 5 => '1', 4 => '0', 3 => '0', 2 =>'1'); a <= (7|5 => '1', 6|4|3|2|1|0 => '0'); a <= (7|5 => '1', others => '0'); a <= "00000000" a <= (others => '0');
IEEE numeric_std package • How to infer arithmetic operators? • In standard VHDL: signal a, b, sum: integer; . . . sum <= a + b; • What's wrong with integer data type?
IEEE numeric_std package libraryieee; use ieee.std_logic_1164.all; useieee.numeric_std.all; • IEEE numeric_std package: define integer as a an array of elements of std_logic • Two new data types: unsigned, signed • The array interpreted as an unsigned or signed binary number signal x, y: signed(15 downto 0); • Need invoke package to use the data type
IEEE numeric_std package:Overloaded Operators
IEEE numeric_std package:New Functions
IEEE numeric_std package:Type Conversion • std_logic_vector, unsigned, signed are defined as an array of element of std_logic • They considered as three different data types in VHDL • Type conversion between data types: • type conversion function • Type casting (for "closely related" data types)
Casting vs. Conversion • Type casting (language primitive) is available between related types • bit, std_logic • bit_vector, std_logic_vector, unsigned, signed • integer, natural, positive • Conversion functions(library add-ons) must be used when type casting is not available. • Best Reference: C:\Xilinx\xx.x\ISE_DS\ISE\vhdl\src.
Non-IEEE Package • Packages by Synopsys • std_logic_arith • Similar to numeric_std • New data types: unsigned, signed • Details are different • std_logic_unsigned/std_logic_signed • Treat std_logic_vector as unsigned and signed numbers • Overload std_logic_vector with arithoperations • Vendors typically store these packages in the IEEE library • Only one type (unsigned/signed) can be used per VHDL file • unsigned/signed defeat the motivation behind strong typing • Inconsistent implementation between vendors • numeric_std is preferred (required in this class)
Synthesis Guidelines
Guidelines for General VHDL Use the std_logic_vector and std_logic instead of bit_vector and bit data types Use the numeric_std package and the unsigned and signed data types for synthensizing arithmetic operations Only use downto in array specification (e.g., unsigned, signed, std_logic_vector) Use parentheses to clarify the intended order of operations Don't use user-defined types unless there is a compelling reason Don't use immediate assignment (i.e., :=) to assign an initial value to a signal Use operands with identical lengths for the relational operators
Guidelines for VHDL Formatting • Include an information header for each file • Be consistent with the use of case • Use proper spaces, blank lines, and indentations to make the code clear • Add necessary comments • Use symbolic constant names to replace hard literals in VHDL code • Use meaningful names for the identifiers • Use a suffix to indicate a signal's special property: • _n for active low signals • _i for internal signals (tied to an output signal to make it readable) • Keep the line width within 72 characters so code can be displayed and printed properly by various editors and printers without wrapping
Lesson Outline Basic VHDL Program Lexical Elements and Program Format VHDL Objects Data Types and Operators Synthesis Guidelines